Apollo 15 Lunar Surface Panorama (AS15-87-11845/47) — NASA. Panorama by Erik van Meijgaarden

Robert D. Schoening

Bob Schoening, BSEE — Electrical Engineer | Software Developer

Decades of test development engineering across disk drives, optical/fiber optics, telecom, networking, embedded systems, PCB design, and data storage — designing production test systems with PXI, GPIB/IEEE-488, I2C, and SCPI instrumentation, managing teams of engineers, programmers, and technicians, and working closely with contract manufacturers.

Military Service (Honorable Discharge)
University (B.S. Electrical Engineering)

All positions were in hardware test dev engineering or engineering management:

NEW YORK, VERMONT

IBM Corporation, Endicott, NY — Computers and circuit boards (PCBs)
IBM / Loral, Owego, NY (formerly IBM, now Lockheed) — Avionics
IBM Corporation, Burlington, VT — Semiconductors

SILICON VALLEY

IBM Corporation, San Jose, CA — Hard disk drives
Harmonic, Sunnyvale, CA — Video delivery technology
Nohau, Campbell, CA — In-Circuit Emulators (ICE)
Vitesse-OSD, San Jose, CA — Optical transponders
Force Computers, Fremont, CA — Embedded computer blades
Ampro Computers, San Jose, CA — Embedded computer boards
Data Domain, Santa Clara, CA — Data deduplication equipment

NEW YORK

BAE Systems, Johnson City, NY — Defense (Contractor, fly-by-wire system)
Consultant, Endicott, NY

Please contact me via LinkedIn for a full resume.

Award: IBM "Outstanding Technical Achievement Award" (OTAA)

A corporate award from IBM for conceiving of and developing a software design tool (TRES, an expert system) that determines the best test plan for unpopulated printed circuit boards (PCBs). TRES (Test/Reliability Expert System) saves 1-2 man years per year and shortened the average test development plan cycle time from 6 weeks to a day. This site had over 5000 employees and its primary business was manufacturing PCBs for a wide variety of IBM products. I conceived of the tool and collaborated with two domain experts in test and reliability (Desai, Hartley) who also shared in award. I led the project and wrote all the software.

Patents: (US 5546321 A, US 5519633 A)

For a second software design tool (MIDAS) that interrelates PCB cross-sectional geometries with electrical performance, manufacturability, cost, test, quality (IFR, ELF, SPQL), and second-level packaging. MIDAS (Manufacturability-Influenced Design Analysis System) cut design times (depending on complexity) from days/weeks to hours. I conceived of the tool, obtained management buy-in, assembled and led a team of 10 knowledge domain experts (named in patent), and wrote all the software.